StarVision™ PRO - Mixed-Signal and Mixed-Language Debugger

RTL-Level, Gate-Level and SPICE-Level in one Integrated Debugging and Visualization Tool — Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats. To support this challenge, Concept Engineering developed StarVision PRO, an integrated debugging cockpit for mixed-signal and digital design that makes analysis and debugging of complex SoC and IC designs easy and more transparent.

Easy Design Exploration — The interactive design navigation window shows schematic fragments of just the critical portion of the design while, at the same time, providing links to the original source code fragments (RTL, Netlist, SPICE) and to simulation results.

• Verilog, VHDL, SystemVerilog, SPICE, HSPICE, ELDO, DSPF, EDIF
• RTL viewer, Netlist viewer and SPICE viewer in one tool
• Mixed-Signal Debugger — Makes IP-based design more transparent
• 32/64-bit database handles today′s largest SoCs and ASICs
• Integrated Waveform Viewer with source code link and schematic link
• Interactive schematic window displays selected fragments and critical paths
• Automatic Logic Recognition — Reads SPICE and shows logic functions
• Tcl based API for user-defined electrical rule checks and customization

Clock Tree Extraction — Clock signals are often a source of problems in complex SoC design. StarVision PRO automatically extracts and analyzes clock trees and gives an immediate view of clock network and clock domains.

Waveform Viewer and Signal Tracing — StarVision PRO comes with a fully integrated waveform browser and with support for interactive signal tracing in the source code, schematic view and waveform window. StarVision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing (accelerated VCD viewer).

Path Extraction — The customizable path extraction engine can automatically identify and extract critical paths in a design. These can be explored and cross-probed in different views to reduce both the complexity and time of the debug cycle.

Automatic Logic Recognition —The built-in automatic logic recognition engine creates digital logic symbols from pure SPICE-level netlists for easy design exploration.

Customization — Users can write API code to analyze the design data and generate user-specific design reports and design checks.

Improved Productivity — Being able to analyze RTL-level, gate-level and transistor-level at the same time in just one debug cockpit increases design and verification engineers productivity, reducing product development time and debug cycle time.

At a Glance

Supported Platforms

Datasheet

Free Evaluation - Software Download

You can register for an evaluation copy of SGvision PRO. When you have your login and password, you can download the tool. For any further information please contact info@concept.de.