Nlview™ Widgets - Automatic Schematic Generation

Concept Engineering's Nlview provides automatic generation of schematic diagrams for different levels of electronic circuits, including Transistor Level, Gate Level, RTL Level, Block and System Level. The schematic layout can be modified and controlled by human intervention and always optimized by algorithms. A fine granularity of user preferences can be mixed with machine computed "beauty" to get the best human readable diagrams. Interactive circuit exploration is supported by incremental schematic generation technology. Nlview provides a set of APIs and interfaces with a certain GUI environment. Please see also the Nlview Widgets data sheet (PDF file).

On this page, please find below: Examples, Widget Family, Good Reasons.

Example Nlview Diagrams

The examples below show Nlview-generated schematic diagrams with comments. The left side shows a cropped pictures, clicking on them will display the full picture.

This simple schematic diagram shows a circuit on operator level with bused connectivity. The connectivity may come e.g. from elaborated Verilog. One way for doing that is using the third-party Verific parser and the VVDI-link that gives Nlview access to the Verific netlist database. The VVDI-link is part of Concept Engineering's Nlview software package.

This schematic diagram shows two highlighted paths and some timing values - as text labels - and some markers (that may have been computed by a third-party tool, e.g. a static timing analyzer). Text labels, markers and highlighting can quickly change without adjusting the schematic layout. However, Nlview can optionally adjust the schematic layout to avoid text overlapping or reuse free space whenever the text labels change in length. For this simple example the loading of the netlist and the generation of the schematic diagram takes about 8ms of CPU time on an old Intel Xeon and the Nlview data-base consumes about 100kB.

This schematic diagram shows two bused muxes with some non-trivial bus connectivity. The rippers are automatically created. The circuit (netlist) given for this example is defined on single-bit level with Nlview performing automatic net bundling from the connectivity (however, the IO port buses and the bus pins of the muxes are given to Nlview).

This incrementally generated schematic diagram shows only a part of the whole circuit: the dashed wires indicate nets or buses that connect more than what is currently displayed. In addition, this example uses a Nlview feature that displays constant values as labels at the pins (here with yellow background) rather than routing power/ground nets to those pins. This example comes from elaborated Verilog, actually from the OpenCores project Aquarius.

This schematic diagram shows two signal paths thru a hierarchical circuit (that may have been extraced by a third-party tool for whatever reason). The different hierarchy blocks are colored differently illustrating some rendering features that Nlview provides, including drop shadow and a sandwich-style stacked appearance. The plus and minus buttons can be used to unfold and fold hierarchy blocks. Nlview can also provide incremental schematic navigation starting with the given diagram. For this example, the loading of the netlist and the generation of the schematic diagram takes about 15ms of CPU time and the Nlview data-base consumes about 80kB.

This schematic diagram is the data-path of the Aquarius OpenCores CPU. This example needs about 55ms for loading the netlist thru Nlview's API and about 220ms for the generation of the schematic diagram (on an old Intel Xeon). The Nlview data-base consumes about 2000kB.

Optional Engines

• T-Engine: Optional Transistor-Level schematic generation engine. More info. Press Release.
• S-Engine: Optional System-Level schematic generation engine. More info.

A Family of Nlview Widgets

Good Reasons for choosing Nlview

At a Glance