GateVision® PRO is the third generation of graphical gate-level
netlist analyzers and netlist viewers from Concept Engineering.
Please check out the Flash Demo:
Completely rewritten to
run on modern 32/64bit platforms, GateVision PRO provides the designer
of even the largest chips and SoCs with intuitive design navigation,
netlist viewing, waveform viewing, logic cone extraction, interactive logic cone
viewing for netlist debugging and design documentation.
Ultra Fast Netlist Viewer — GateVision PRO is an ultra fast
and extreme capacity gate-level netlist debugger and netlist viewer reading and
processing even the largest Verilog netlists, EDIF netlists and LEF/DEF
Reading Verilog, EDIF and LEF/DEF netlists, GateVision PRO fits seamlessly into
any design environment. Schematics are generated on the fly and the intuitive
GUI lets the designer incrementally and easily navigate through the largest
- Extreme performance netlist viewer for Verilog, EDIF, and LEF/DEF
- Tcl based UserWare API — for advanced customization
- 32/64 bit database handles today′s largest SoCs, ASICs and FPGAs
- Integrated Waveform Browser (accelerated VCD viewer)
- Customizable path extraction engine finds critical paths
- Cone view displays schematic fragments of critical areas
- Intuitive GUI for ease of use
API — a tcl based UserWare API provides full access to the new
32/64-bit based database, for highly flexible customization. The designer
can extend the
functionality of GateVison PRO to meet the immediate needs of the project,
adding, for example, electrical rule checking (ERC), report and documentation
functions. The API also allows GateVison PRO to be closely integrated with
different design flows and third party tools.
Waveform Viewer and Signal Tracing — GateVision PRO comes with a fully
integrated waveform viewer and with support for interactive signal tracing
in the source code, schematic view and waveform window. GateVision PRO compiles
VCD simulation data into its own high-speed format for accelerated waveform
browsing and signal tracing.
32/64 Bit — exploiting the increasing powerful 64 bit platforms,
Intel Xeon, Intel Core, AMD Opteron and AMD Phenom, GateVision PRO runs
quickly and efficiently, even for the largest and most complex of
today′s demanding ASICs, SoCs and FPGAs. The underlying database
has been completely redesigned for 32/64-bit operation.
Logic cone — the GateVision PRO logic cone view provides interactive navigation within a schematic fragment, that portion of the circuit that is most relevant. This can be extended and reduced for signal path tracing through the complete design hierarchy.
Path extraction and Verilog Simulation — The customizable path
extraction engine can automatically identify and extract critical paths in a design.
These can be explored and cross-probed in different views to reduce both the
complexity and time of the debug cycle. Path fragments can be exported as Verilog
netlists for critical path Verilog simulation.
GUI — the intuitive GUI provides a host of facilities including
context sensitive menus and multiple views. A powerful search tool provides
quick access to any object or group of objects in a design, with the results
stored in a result list. Listed objects can be highlighted or moved into the
logic cone window.
Debugging Views — Built into GateVision Pro are a variety of
view options, including schematic view, schematic fraction view, source code view,
hierarchy tree view, waveform view, clock domain view, and object search view.
Through these, and through cross-probing between views, it is easy to gain a deeper
understanding of the device being debugged and to improve the debugging process.
At a Glance
Ultra fast netlist readers
Netlist to schematics on the fly (within seconds)
Higher performance and increased capacity, for very large designs
Integrated waveform viewer
For easy signal tracing and simulation results analysis (accelerated VCD viewer)
Automatic clock tree and clock domain extraction and visualization
Faster detection and resolution for clock domain problems
Incremental schematic navigation for big designs
Verilog Netlist Export
Fragments of a circuit can be saved as Verilog netlist files
Tcl UserWare API
Allows interfacing with tool flow and definition of electrical rule checks
Netlist to schematics
Verilog viewer, EDIF viewer, and LEF/DEF viewer in one tool allows debugging
of almost any netlist file format
Multiple views, including tree, schematic, waveform, cone and source file for
increased circuit understanding plus drag-and-drop between different views.
Automatic path extraction
Automatically extracts logic cones from user-defined reference points, and shows only the relevant portion of the circuit, Reduces complexity in the design for improved and faster netlist debugging
Easy location of specific objects shortens debug time
Design hierarchy browser
Provides easy navigation through the design hierarchy and gives compact hierarchy overview
Highlights selected objects in all design views (schematic, logic cone and HDL
source code view) and shortens debug time
Please click to see the supported platforms.
Click here to get a PDF file of our
GateVision PRO datasheet.
Free Evaluation - Software Download
for an evaluation copy of GateVision. When you have
your login and password, you can
download the tool.
For any further information please contact