T-engine™ - Transistor-Level Schematic Generator
The Nlview™ basic engines automatically generate schematics at the gate, register-transfer, block and system level. With the T-engine option, Concept Engineering provides advanced visualization technology to EDA tool developers who develop tools for the transistor-level (or device level). When integrated with EDA tools, Concept Engineering's T-engine helps designers of electronic integrated circuits (ICs) and systems on a chip (SoCs) to visualize such critical information as circuit structure, parasitic components, timing data and signal values at the transistor level, so they can more easily and accurate tune designs for maximum performance. T-engine also makes it easier to understand output results of cell and IP-block characterization tools.
In response to demand from the electronic design automation (EDA) and the semiconductor industries, Concept Engineering has developed completely new transistor-level algorithms that generate easy-to-read schematics. T-engine recognizes common device-level circuit patterns, and can detect and analyze serial/parallel circuit paths. It also can perform current flow analysis (i.e., power-to-ground flow) and logic flow analysis including both left-to-right flow and reverse-flow detection for feedback. In addition, T-engine uses new place-and-route techniques developed by Concept Engineering. As a result T-engine is able to produce clean transistor-level schematics for complex transistor designs. In addition Concept Engineering's new schematic engine also supports a mix of transistor-level technology with gate-level or block-level technologies in a single schematic diagram.
Concept Engineering's automatic transistor-level schematic generation engine is available as an optional engine to the Nlview Widget Product Family.
At a Glance
Widest Platform Availability
DatasheetClick here to get a PDF file of our T-engine datasheet.
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Last Modified: 2014/01/24.