RTLvision® PRO provides easy RTL debugging and fast visualization of RTL code, so that engineers can easily understand, implement and optimize VHDL, Verilog or SystemVerilog code. Please check out the Demo Videos: Basic Features and Clock Tree Analyzer.
With rising chip complexity it is no longer possible to carry out all ASIC and SoC designs from scratch: RTL code elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding VHDL or Verilog source code for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.
All RTL Languages - One Debugging Cockpit — RTLvision PRO is a powerful easy to use RTL viewer who combines Verilog viewer, VHDL viewer and SystemVerilog viewer in one single integrated debugging cockpit.
Clock Tree Extraction — Clock signals are often a source of problems when integrating RTL code elements from different sources; RTLvision PRO automatically extracts and analyzes clock trees and gives an immediate view of the clock network and clock domains.
Interactive RTL code navigation — RTLvision PRO can read HDL (Hardware Description Language) and display the underlying circuits on the fly, providing the engineer with immediate understanding of functionality of the RTL description. To accelerate debugging, critical code portions can be graphically displayed in the Logic Cone Window: the engineer can concentrate on that critical fragment, with links to the original HDL source code, while not bothering about other areas of the design.
Waveform Viewer and Signal Tracing — RTLvision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window. RTLvision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.
Documentation — The automated documentation feature of RTLvision PRO provides detailed design documentation of new, changed and re-used RTL code (Verilog schematic view, VHDL schematic view, PDF output, Postscript output, bitmap image).
Customization — To meet the needs of a specific project or an organization's own standards a Tcl based UserWare API allows the functionality of RTLvision PRO to be extended and tailored.
|Ultra fast Verilog reader, VHDL reader and graphics on the fly||Graphical representations make it easier to understand, debug, change and implement VHDL, Verilog and SystemVerilog code|
|Interactive Graphic Fragment Navigation shows only critical fragments of the RTL code||Being able to identify and concentrate on a fragment helps to reduce complexity of the debug process and makes it easier to understand and change RTL source code|
|Automatic clock trees and clock domains extraction and analysis||Faster detection and resolution of clock domain problems. CDC view shows clock domain trees.|
|Integrated Waveform viewer||VCD Waveform viewer supports interactive signal tracing|
|Full support for mixed language designs (SystemVerilog, Verilog, VHDL)||Designers can easily develop and debug today's most complex heterogeneous SoC designs|
|Incremental design compilation||Design updates can be faster, with only changed areas re-compiled|
|RTL to schematics||Verilog viewer, VHDL viewer, and SystemVerilog viewer in one tool allows building blocks from almost any source to be analyzed|
|Automated design documentation||New and re-used code can be documented automatically|
|Tcl API||RTLvision PRO can be interfaced with the tool flow and the user can extend functionality to match project needs|
Click here to get a PDF file of our RTLvision PRO datasheet.