RTLvision® PRO - Visualize, Debug and Integrate RTL Code, Easily

RTLvision® PRO provides fast visualization of RTL code, so that engineers can easily understand, implement and optimize RTL code, whether in VHDL, Verilog or SystemVerilog. Please check out the Flash Demos: Basic Features and Clock Tree Analyzer.

With rising chip complexity it is no longer possible to carry out all ASIC and SoC designs from scratch: RTL code elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding VHDL or Verilog source code for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.

All RTL Languages - One Debugging Cockpit — RTLvision PRO is a powerful easy to use RTL viewer who combines Verilog viewer, VHDL viewer and SystemVerilog viewer in one single integrated debugging cockpit.

• Understand high-level designs: Fast Verilog and VHDL visualization makes legacy RTL code and IP code easy to understand, debug, modify and integrate
• Mixed language capability: Support for SystemVerilog, Verilog and VHDL matches the demands of today's complex heterogeneous ASIC and SoC designs
• Interactive fragment navigation: Logic Cone Window displays a visualization of just critical sections of RTL/HDL linked to original source code
• Tcl based UserWare API: access to database and GUI for project-specific or company-specific customization

Clock Tree Extraction — Clock signals are often a source of problems when integrating RTL code elements from different sources; RTLvision PRO automatically extracts and analyzes clock trees and gives an immediate view of the clock network and clock domains.

Interactive RTL code navigation — RTLvision PRO can read HDL (Hardware Description Language) and display the underlying circuits on the fly, providing the engineer with immediate understanding of functionality of the RTL description. To accelerate debugging, critical code portions can be graphically displayed in the Logic Cone Window: the engineer can concentrate on that critical fragment, with links to the original HDL source code, while not bothering about other areas of the design.

Waveform Viewer and Signal Tracing RTLvision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window. RTLvision PRO compiles VC simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.

Incremental compilation — RTLvision PRO can visualize VHDL, Verilog and SystemVerilog code, matching the needs of today's most complex heterogeneous designs. It also supports incremental compilation, re-compiling only those areas that are affected by change, further reducing development time.

Documentation — The automated documentation feature of RTLvision PRO provides detailed design documentation of new, changed and re-used RTL code (Verilog schematic view, VHDL schematic view, PDF output, Postscript output, bitmap image).

Customization — To meet the needs of a specific project or an organization's own standards a tcl based UserWare API allows the functionality of RTLvision PRO to be extended and tailored.

At a Glance

Features	Benefits
Ultra fast Verilog reader, VHDL reader and graphics on the fly	Graphical representations make it easier to understand, debug, change and implement VHDL, Verilog and SystemVerilog code
Interactive Graphic Fragment Navigation shows only critical fragments of the RTL code	Being able to identify and concentrate on a fragment helps to reduce complexity of the debug process and makes it easier to understand and change RTL source code
Automatic clock trees and clock domains extraction and analysis	Faster detection and resolution of clock domain problems
Integrated Waveform viewer	Waveform viewer supports interactive signal tracing
Full support for mixed language designs (SystemVerilog, Verilog, VHDL)	Designers can easily develop and debug today's most complex heterogeneous SoC designs
Incremental design compilation	Design updates can be faster, with only changed areas re-compiled
RTL to schematics	Verilog viewer, VHDL viewer, and SystemVerilog viewer in one tool allows building blocks from almost any source to be analyzed
Automated design documentation	New and re-used code can be documented automatically
Tcl API	RTLvision PRO can be interfaced with the tool flow and the user can extend functionality to match project needs

Supported Platforms

Please click to see the supported platforms.

Datasheet

Click here to get a PDF file of our RTLvision PRO datasheet.

Free Evaluation - Software Download

You can register for an evaluation copy of RTLvision PRO. When you have your login and password, you can download the tool. For any further information please contact info@concept.de.