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Concept Engineering GmbH |
SGvision™ PRO |
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SGvision™ PRO is a new tool to analyze mixed level
descriptions, both top level structures described in Verilog and lower level
structures described via SPICE, can be debugged in a single integrated
environment.
To optimize or debug a device a designer may choose to work at transistor-level for critical areas such as IP/Library components and analog blocks, while staying at gate-level for other areas of the design. Debugging such a design has previously required separate tools: with SGvision PRO, it is now possible to see the schematics and traverse the signal flow of both the gates and the transistors in the same window, improving understanding of the circuits and accelerating analysis and debugging.
Tcl based API — he Tcl Based UserWare API provides very flexible customization options, allowing SGvision PRO to match individual needs, corporate standards or to be integrated into an organizations design flow. Customer driven — users of the existing Concept Engineering debugging tools, GateVision® PRO for gate-level and SpiceVision® PRO for transistor-level, have asked for a single interface for mixed level debugging. SGvision PRO provides just this tool, combining two tools in one for flexibility and power in debugging. 32/64 bit — SGvision PRO runs on powerful 64 bit platforms, such as UltraSPARC, Opteron, Itanium and Xeon. The underlying database, specially developed for 32/64 bit operation, allows even the most complex of today's SoC and ASIC designs to be examined. Documentation — The automated documentation feature of RTLvision PRO provides detailed design documentation of new, changed and re-used code, all to the same standard. Circuit fragment debugging — the Logic Cone Window is an intelligent magnifying glass, allowing the engineer to concentrate on a specific circuit fragment or critical path, showing both gate- and transistor-level details in a single window. There is no distraction from irrelevant graphics and information, yet there are links to the source code, whether Verilog or SPICE. The fragment under investigation can be independently exported as a SPICE netlist and can be used for the fast simulation of critical circuit fragments. It is not necessary to simulate the whole design, reducing simulation and development time drastically. Improved productivity — being able to analyze both gate-level and transistor-level at the same time in just one debug cockpit increases design and verification engineers productivity, reducing product development and debug cycle time. At a Glance
Supported PlatformsPlease click to see the supported platforms.DatasheetClick here to get a PDF file of our SGvision PRO datasheet.EvaluationYou can register for an evaluation copy of SGvision PRO. When you have your login and password, you can download the tool. For any further information please contact info@concept.de. |
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Copyright © 2009 by
Concept Engineering Last Modified: 2010/06/14.
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