SGvision™ PRO - Gate-Level and SPICE-Level Visualization and Debugging

SGvision™ PRO is a new tool to visualize and debug mixed level descriptions, both gate-level structures described in Verilog and transistor-level structures described via SPICE, can be debugged in a single integrated environment.

Gate-Level and Transistor-Level visualization and debugging in a single tool — To optimize or debug a device a designer may choose to work at transistor-level for critical areas such as IP/Library components and analog blocks, while staying at gate-level for other areas of the design. Debugging such a design has previously required separate tools: with SGvision PRO, it is now possible to see the schematics and traverse the signal flow of both the gates and the transistors in the same window, improving understanding of the circuits and accelerating analysis and debugging.

• Mixed mode graphical analyzer — Verilog and SPICE in a single tool.
• As detailed as you want — Debugging at gate-level and transistor-level.
• Logic cone — debug selected fragments or critical paths.
• 32/64 bit database — handles the largest SoCs and ASICs.
• Tcl based UserWare API — for advanced customization.
• Cookie cutting — critical SPICE fragments can be isolated and saved as separate SPICE files.

Tcl based API — The Tcl based UserWare API provides very flexible customization options, for example customer defined electrical rule checks, allowing SGvision PRO to match individual needs, corporate standards or to be integrated into an organizations design flow.

Customer driven — Users of the existing Concept Engineering debugging tools, GateVision® PRO for gate-level and SpiceVision® PRO for transistor-level, have asked for a single integrated tool for mixed-level debugging. SGvision PRO provides just this tool, combining two tools in one for flexibility and power in mixed-mode debugging.

32/64 bit — SGvision PRO runs on powerful 64 bit platforms, such as Xeon, Phenom, Opteron, PowerPC, UltraSPARC and Itanium. The underlying database, specially developed for 32/64 bit operation, allows even the most complex of today's SoC and ASIC designs to be examined.

Automatic Logic Recognition — With its built-in automatic logic recognition engine SGvision PRO automatically creates and displays digital logic from pure SPICE-level netlists for easy design visualization and exploration.

Documentation — The automated documentation feature of SGvision PRO provides detailed design documentation of new, changed and re-used code, all to the same standard.

Circuit fragment debugging — The Logic Cone Window is an intelligent magnifying glass, allowing the engineer to concentrate on a specific circuit fragment or critical path, showing both gate- and transistor-level details in a single window. There is no distraction from irrelevant graphics and information, yet there are links to the source code, whether Verilog or SPICE. The fragment under investigation can be independently exported as a SPICE netlist and can be used for the fast simulation of critical circuit fragments. It is not necessary to simulate the whole design, reducing simulation and development time drastically.

Improved productivity — Being able to analyze both gate-level and transistor-level at the same time in just one debug cockpit increases design and verification engineers productivity, reducing product development and debug cycle time.

At a Glance

Features	Benefits
Support for Verilog, EDIF and SPICE dialects. Netlist Viewer and SPICE Viewer in a single tool.	Engineers can quickly and easily understand and debug mixed-signal designs. SPICE dialects include: SPICE, HSPICE, Calibre, CDL, Eldo and PSPICE. Netlist support for: Verilog, EDIF and LEF/DEF.
Automatic logic recognition	The built-in automatic logic recognition engine creates digital logic symbols from pure SPICE-level netlists for easy design exploration.
Ultra fast Netlist and SPICE viewer	Netlist to schematics on the fly (within seconds).
Fragment save	Fragments of circuits can be saved as SPICE file and schematic for future reuse as IP, or for partial simulation
Parasitic analysis option	Allows visualization and analysis of paraitic networks (DSPF) and provides capabilities to create SPICE netlists for critical parasitic network fragments.
Support for Verilog and SPICE dialects in a single tool	Engineers can quickly and easily understand and debug mixed-mode designs (SPICE,Verilog, EDIF)
Interactive graphic fragment navigation	Reduces debug complexity and increases engineering productivity
Object cross-probing	By highlighting objects in all design views (schematic, logic cone and source code), helps shorten design and debug time
Tcl UserWare API	Allows user customization and interfacing to the design tool flow
32/64 bit platform support	Power to cope with the largest mixed-mode SoCs and ASICs
Non-Parasitic view	Displays CMOS function without parasitic structures for comprehension of circuit
Predefined symbols	Symbols for all gate-level and Spice-level primitives are built-in. External symbol libraries are supported. As a result schematics are easy to read and easy to understand.

Supported Platforms

Please click to see the supported platforms.

Datasheet

Click here to get a PDF file of our SGvision PRO datasheet.

Free Evaluation - Software Download

You can register for an evaluation copy of SGvision PRO. When you have your login and password, you can download the tool. For any further information please contact info@concept.de.