Concept Logo
 

We make things visible®

We provide visualization and debugging technology for electronic circuits and systems, including schematic generation for all major design levels. Our technology helps electronic design engineers to easily understand, debug, optimize and document electronic designs. Please check out our products for electronic design engineers and for EDA tool developers. Our software technology is used in many fields in the EDA market, including: RTL development, IP reuse, ASIC and SoC design, FPGA design, analog/mixed-signal design, logic synthesis, design verification, test automation, post-layout analysis, debugging and visualization on system level, RTL level and netlist level.

Upcoming Events

SEMISRAEL 2014SemIsrael Expo 2014
Avenue Convention Center at Airport City, ISRAEL
November 25, 2014

Our products will be presented by our distribution partner KAL Katav Associates Silicon Technologies Ltd.

News

Concept Engineering Introduces S-engine™: Automatic System-Level Schematic Generation Capabilities Combined with IP Editing and Assembly

Freiburg, Germany - May 22, 2014 - With S-engine, Concept Engineering introduces a radically new concept of system-level visualization and smart editing technology. EDA tool manufacturers can now easily create modern system-level and IP-centric design and visualization tools. Press Release.

Connectivity Package Links Concept Engineering, Verific Design Automation Tools

Freiburg, Germany, and Alameda, California - May 1, 2014 - Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of connectivity package that links Concept Engineerin′s Nlview™ schematic generator and visualization engine with Verific's netlist database. Press Release.

More Success Stories / Customers

Check out our Press Archive to see why leading EDA vendors and semiconductor companies choose our advanced visualization and debugging technology to power their EDA tools and improve their design flows.