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We make things visible®

We provide visualization and debugging technology for electronic circuits, including schematic generation for netlists typically available with logic synthesis, verification, test automation and physical design tools. Our technology helps electronic design engineers to easily understand, debug, optimize and document electronic designs. Please check out our products for electronic design engineers and for EDA tool developers. Our software technology is used in many fields in the EDA market, including: RTL development, IP reuse, ASIC and SoC design, FPGA design, Analog mixed-signal design, synthesis, verification, post-layout analysis, debugging and visualization on system-level, RTL-level and netlist-level.

Upcoming Events

We are looking forward to meeting you at one of these events.

ChipEx 2014ChipEx 2014, Tel Aviv, Israel, April 30, 2014
Israel Trade Fairs & Convention Center

DAC 2014Design Automation Conference (DAC 2014), San Francisco, CA, June 2-4, 2014
Moscone Center, Booth 1201


Concept Engineering Adds SPEF Parasitic Netlist Interface to SpiceVision® PRO and StarVision® PRO

Freiburg, Germany - May 28, 2013 - Concept Engineering has added a new SPEF (standard parasitic exchange format) interface to their widely-installed debugging tools, SpiceVision® PRO and StarVision® PRO. SpiceVision PRO takes SPICE netlists and SPICE models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, circuit debugging and circuit optimization at the transistor level. StarVision PRO, an integrated debugging cockpit for Mixed-Signal design, makes analysis and debugging of complex SoC (system on chip) and IC (integrated circuit) designs easy and more transparent. Press Release.

More Success Stories / Customers

Check out our Press Archive to see why leading EDA vendors and semiconductor companies choose our advanced visualization and debugging technology to power their EDA tools and improve their design flows.