Concept Engineering Releases GateVision® PRO – a Debugging Tool for the Verification of Complex Chips
New GateVision PRO gives designers more control over gate-level debugging of ICs, SoCs, IP blocks, FPGAs
Design Automation Conference, Anaheim, Calif. – June 13, 2005 – Concept Engineering GmbH today announced GateVision PRO, a gate-level debugging tool that offers higher performance and an open application programming interface (API) that allows chip designers to customize and implement their own debugging functions. In addition, a new 64 bit database provides higher capacity, giving chip design teams the ability to debug large, complex chips.
"The higher complexity of today's chips has created the need for debugging tools with higher performance and capacity," said Gerhard Angst, Concept Engineering CEO. "GateVision PRO offers our customers many ways to solve problems in their existing design flows, and brings gate-level debugging to the next level."
GateVision PRO fits easily into any design flow where Verilog and EDIF netlist formats are being used. The new product gives designers of integrated circuits (ICs), systems-on-chip (SoCs), intellectual property (IP) blocks, and complex field-programmable gate arrays (FPGAs) full access to the chip database. Such a capability is useful for integrating GateVision PRO into different design flows, as well as for writing custom electrical rule checkers (ERC), report functions, and data consistency checks. Designers can also visualize information from side files within GateVision PRO schematics.
"To verify our high end chips we needed a very special custom extraction method to find and isolate certain critical paths within our designs," said Masami Kinoshita, executive professional of DA Technology Gr. at Elpida Memory, Inc. (Tokyo, Japan). "Based on the customizable path extraction engine in GateVision PRO, we were able to automatically extract these paths and improve error coverage in our verification flow."
More about GateVision PRO
Features of the new GateVision PRO include:
- UserWare API for easy flow integration and customization of functions such as report generation and ERCs.
- High performance, high capacity.
- A new database design with an open API interface provides full access to the database objects.
- 64-bit platform support to handle the most complex chips. Supported platforms include Sun UltraSPARC processors on Solaris, AMD Opteron processors on Linux, Intel® EM64T processors on Linux, IBM POWER4+ processors on AIX, and Intel Itanium 2 on Linux.
- Automatic path extraction that enables designers to extract critical paths in a design. This reduces the complexity of the debug problem and accelerates the debug process.
- Debugging features – such as schematic view, schematic fragment view, source code probing, hierarchy tree view, and object search view – enable designers to quickly understand, optimize and debug complex chips.
Price and Availability
GateVision PRO is available now. Pricing details can be obtained by contacting Concept Engineering and its distribution partners via www.concept.de.
About Concept Engineering
Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company's customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information see www.concept.de
Contacts:
Concept Engineering
Gerhard Angst, +49-761-47094-0, info@concept.de, www.concept.de
Cayenne Communication LLC for Concept Engineering
Michelle Clancy, +1-252-940-0981, michelle.clancy@cayennecom.com